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operations on data not encoded in the regular 16-bit, two's complement integer form of the RTM system. (The shifting problem of Chapter 3 contains a discussion of two's complement representation.)

There are other forms of binary encoding for signed numbers such as sign- magnitude and one's complement (see the shifting problem in Chapter 3) which will be discussed only briefly here. Logical design texts, enumerate these other forms. They are omitted from extensive discussion both because most digital systems use the two's complement encoding and because we simply cannot be all-inclusive. The principal reason, though, for discussing two's complement operations is that RTM's were designed to facilitate arithmetic on data in this form.

Two's complement numbers will be presented in two forms: single word precision -- one 16-bit word; and n-word precision -- n 16-bit integers concatenated to form an n*16-bit word with the sign bit held in the most significant bit of the most significant word. The n-word case is presented for the sake of generality. Two-word (double) precision, which is sufficient for most applications, is readily derived from the n-word case. Using both the one-word and n-word forms, subprocesses are given to perform addition, subtraction, complementation (negation), shifting, and multiplication. These subprocesses are easily understood and will be discussed only briefly. The problem-statement format used for most examples in this book will be returned to for the description of more complex subprocesses.

The binary coded decimal(BCD) encoding scheme using the 8421 code is presented since it is often needed outside the RTM system for devices used in human communications (lights, switches) and for some instrumentation transducers (e.g., shaft position indicators, digital voltmeters). BCD addition and conversion algorithms for BCD-to-binary and binary-to-BCD are given.

A short section presents the scientific notation (floating point) representation, which is used for data that varies over a wide exponent range. The section will introduce the problem of implementing floating point operations but will not give detailed solutions.

DATA PART FOR THE ARITHMETIC OPERATIONS

In the design of the data operations subprocesses, a particular fixed structure for the data part of the system will be used. In this way, the operations can be considered as a collection of subprocesses, all of which operate with a common memory and arithmetic unit; Figure DATA-1 shows the common data part. Two scratch pad memories, S[0:15] and T[0:15] hold the operands. The arithmetic operations are performed in the A and B registers of the DMgpa. Register S[0] is used for monadic (unary) operations of the type, S[0]<- u(S[0]), e.g., shifting, incrementing, complementing, etc. The form for the dyadic (binary) operations is S[0] <- b(S[0],T[0]), which includes operations such as addition, subtraction, multiplication, etc. which require two operands. For n-word precision operations, registers S[n-1],...,S[0] and T[n-1],...T[0] hold the operands (most significant part to least significant). Note, however, that in some cases T might merely be a renaming of some of the registers in S. For example, using double precision, S[1] and S[0] might hold the first operand and S[3] and S[2] hold the second, then T[1]:=S[3] and T[0]:=S[2].

Since the arithmetic operations are carried out in the A and B registers of the DMgpa, extra operations are required to load the operands from S and T and store the results back. A DMflag is used to hold carry information, Carry Flag\CF, in some of the multiple precision operations and it is also used as

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