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Fig. 29. Subroutine for multiplication using RP algorithm for PDP-16/M.

Even before making a quantitative estimate of the operation time, an important feature of the organization of small minicomputers can be seen directly from Figure 30. Since they only have a single arithmetic register (A) with the second operand coming from the primary memory, they require a large number of operations to load and store data. This is apparent from a horizontal comparison between the righthand side, expressing the essential computation, and the code, along the lefthand side. This extra quota of operations, which occurs throughout all .the code, creates another factor of speed degradation to be multiplied in with the factor already present for accessing of control steps from memory and the interpretation loop for decoding each control step once obtained.


We now have three distinct software organizations to be compared, both against each other and against a hardwired organization. Rather than make that comparison in this subsection, it will prove worthwhile to step back and examine generally all of the solutions that we have obtained in the chapter.

Before we leave this implementation, however, it is worth noting that there is no single hardware-software tradeoff, but rather an entire spectrum of implementations, both on the hardwired side (which one might expect) but also on the software side, defined as those implementations that encode the control part of the algorithm into memory. Putting forth three distinct software implementations was done, in part, to make this point. In fact, we could have proceeded through at least two more stages. One would be a mini-computer organization where a multiply-step of some kind was given as a primitive


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