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Chapter 6 describes a small computer, the PDP-16/M, which consists of a particular collection of RT modules in which a fixed set of control operations have been preassigned in terms of a fixed data part. Only a certain subset of all possible transfers for the particular data part can be given. The control part is a, K(PCS), so that the program is the set of control steps that are placed in the primary memory of the K(PCS).

The instruction set of the C(16/M), being identical in form to that of the K(PCS), is similar to the instruction sets typical in microprogramming. Thus, we can refer to the C(16/M) as a microprogram or microcode computer, to distinguish it from computers with conventional instruction formats, involving N- addresses, indexing, general registers, and various other addressing modes. Terminology is still unsettled in the microprogramming area, since the term microprogrammed computer refers not at. all to the nature of the computer's instruction set, but to the fact that its interpreter is realized through another - computer, which interprets a code of its own (the microcode). Thus to call a computer a microcode computer is only describing it indirectly by means of a family resemblance to other computers which occur in a certain application (i.e., microprogramming). But the C(16/M) stands on its own as a particular small computer.

The program for the RP algorithm coded into the 16/M is given in Figure 29. It is similar to the hardwired version in Figure 24, since the 16/M uses only a single DMgpa. Consequently, extra memory transfers are required. The operation time required is longer than for the prior case, where the data structure could be adapted to the algorithm at hand. Thus, the preselection of a fixed set of data operations implies some costs to be paid later when particular algorithms are to be coded. The cost, by the way, is an opportunity cost (to use a phrase from economics), since it only shows up in terms of alternative organizations that were not available. If two DMgpa's were included in the 16/M, then real costs would be accrued in all those applications where only one (or none) DMgpa was used For then actual equipment would be sitting idle.


Multiplication is carried out using subroutines in some small minicomputers. One, called Crtm-1, is described in Chapter 6. We can use it to provide a third example of a software realization of multiplication. It differs from C(16/M) and from K(PCS) in having a typical minicomputer one-address instruction set.

In Figure 30, we show the subroutine for multiplication coded for the computer. We give it in three representations, since we have not formally defined the machine here. The lefthand side gives the code, in conventional assembly language format: the instruction location label (if it exists), followed by the operation code, followed by the address (or other argument, on occasion). In the center we give the equivalent ISP statements. The meaning of the operation codes can rather easily be inferred from this representation. The righthand side gives a flowchart for the algorithm in the style we have been using throughout.

This computer could be implemented either with a hardwired control part or with a K(PCS), which would make it a microprogram computer. Between the two there is a speed-cost trade-off of roughly a factor of two in speed for roughly a factor of two in cost. Which choice is taken clearly effects the performance of the total system as a multiplier. Better stated, it provides two separate points on a cost-speed trade-off curve, to be compared against the points for C(16/M) and K(PCS).


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