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below that predicted from the operation time. A common example in memory technology occurs in magnetic core random access memories, which deliver the contents of the addressed work in, say, .9 microseconds, but require another .4 microseconds to finish the rewrite cycle. This gives an access time of .9 and an access rate of 1/1.3, equivalent to 770,000 accesses per second, compared to a "predicted" 11.9 or 1,110,000 accesses per second. Often only one of these two performance measures is important, but only an analysis of the larger system can tell.

SUMMARY

We have devoted this section to examining how a subsystem, such as multiplication, might occur in a larger algorithm. Several alternatives almost always make themselves felt at the RT-level of design: minimizing the hardware by using subroutining; mapping each occurrence into separate hardware (macros); speeding up the algorithm by pipelining; and maximizing speed by complete duplication of hardware for independent operations (array parallelism). These alternatives provide a set of trade-offs between hardware (cost) and speed, though where each alternative stands in the trade-off (how much hardware for how much speed) depends on the details of both the subsystem and the larger system in which it occurs. Only detailed analysis can reveal the

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