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a DO loop causes a one time execution of the DO loop, they become slightly critical about meaning and consistency. Here, however, the problem is not just that 0 produces no actions; it is stilt necessary to check for a zero case prior to entering the loop, even if the loop detects 0 indexes prior to executing the loop. The following two solution implementations point this out.


In Figure CD-2e the testing for n=0 is performed before entering the loop, using the for loop ERTM previously described. Waiting for the clock will occur no times if n is 0. The structure has a more consistently defined behavior than Solutions 1 and 2 because the for loop is executed in a short time, generating a very large number of outputs per unit of time. The rate is uncontrolled, however, being determined by the time taken by the for loop control. That is, when n is 0 the part that synchronizes with the clock is never evoked. Somehow, this type of action also seems strange when compared with the behavior of a program. The difference can be seen between this case and that of programming; in programming one is interested in the number of times a process is to be executed and less interested in the control part (i.e., a program). Here the' number of times a process completes is of interest and the control structure completion is giving erroneous outputs.


Figure CD-2f finally solves the problem again, by first checking whether n is 0 before starting the for loop. In this way, erroneous outputs for this case are not generated. This rather lengthy discussion of five designs, only two of which are correct, illustrates concepts of number representation, loop control, and inter-process synchronization. In addition, it illustrates how a problem often becomes totally specified only when the design is carried out.


1. Design a K(programmable clock) which has only one control part (instead of two) that is activated from the K(clock; period: T'). A DMflag (Clock-Event) might not be used, but instead each occurrence of the clock would cause the status of n and i to be checked and updated. Output control events would be given each time i is counted down to zero.

2. K(programmable(variable)delay). - A K(programmable delay) can be constructed which is similar to the K(programmable clock). The overall structure of such a device is given in Figure CD-3. The behavior is like the standard K(delay) of Chapter 2.

3. Design a clock that has two control parts that are similar to the control parts used in the K(clock) above. Determine the average delay time as a function of the input delay time, n. Take care to avoid a solution which has the behavior of (n,t) as (0,0), (1,0), (2,0~1), (3,1~2)...(n,n-2~n-1).

4. Design a delay with two control parts which uses the time base generator to cause the output activate-next signals as in the control part case of problem 1 above. The counting process is started by a flag set by the activate input which indicates that a time period is to be measured.

5. Design a K(integrating programmable delay) which is similar to that given in Chapter 2.


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