ADDITIONAL PROBLEMS

1. What value is output in case of overflow? Is it the same value for all inputs that are large enough to create an overflow? What is the largest N for which the system can compute F(N)? Given this value of N, is it clear why only one check was made for overflow in Solution 2?

2. Cost out the three proposals. Discuss the tradeoff between cost and speed. Why does it come out this way?

3. Is there a direct formula for calculating F(N)? Find one and determine whether it provides an alternative basis for computing F(N).

4. Suppose you had only 8 words of memory available (say as part of a larger core memory devoted to a total system). What sort of a fast Fibonacci generator could you build? Where would it come on the cost-speed graph of Problem 2?

KEYWORDS: Counting, clock, delay, integrating delay, wait-until, time-base, synchronization

The period T' of the basic RTM K(clock) described in Chapter 2 is a constant, or more precisely, a variable which is set by a manual potentiometer adjustment. It seems desirable to have another kind of clock that has a period T that can be specified dynamically by a parameter from within an RTM system.

PROBLEM STATEMENT

Design a clock, using RTM components, that has a variable period T that can be set by an RTM system.

DESIGN CONSIDERATIONS

The proposed clock might have an overall RTM structure such as that shown in Figure CD-1. It would use a basic RTM ((clock) of constant period T' as an input. It would also have an input word, n, to specify the period T as a multiple of the base period T', i.e., T = n*T', where n = 0,1,2,...,n-max. The clock would give an output control signal for each n counts of the basic clock, which has period T'. We can assume that n is held outside the system and is Accessible via a T(input interface).

Fig. CD-1. Module diagram of K(programmable (variable) clock).

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