available. One is a variation of the Dmgpa, and the other is a variation of the Kbus. Because of the importance of these modules we include a description of them here. However, because of their late arrival, none of the examples in the book utilizes these modules.

__DM(arithmetic and registers)\DMar__. Two modules, the DM(arithmetic register unit)\DMaru and the K(function encoder)\Kfe, taken together form a module which will be designated as the DM(arithmetic and registers)\DMar Although the Dmaru can conceivably be used alone, the two modules will most likely be used together, hence they will be described together. Figure 24 describes the DMar, and should be consulted during the following description.

Briefly speaking, the DMar is much like a DMgpa with 16 addressable B registers, and the ability to receive encoded as well as direct evoke inputs for its functions. Actually, the DMar has 17 + 5/16, 16-bit registers available: A<15:0>, a 16 word scratchpad M[0:15]<15:0>, and 5 bits of the last result loaded into any of the positions of the scratchpad, designated r<15, 3:0>. Like the DMgpa, most operations are carried out on A. For operations on two registers, the second operand is held in the 16-word memory, M. The specific word of M is selected by a 4-bit input, X<3:0>, thus operations are actually on M[X]. Since all 16 combinations of X<3:0> are used, they may be addressed with either positive or negative logic. Thus, for example, they may be addressed using a Kevoke. Four NOR gates are provided on the Kfe to expand the inputs to X<3:0> if necessary.

DMar has essentially the same functions provided by DMgpa, with the exception that M[X] appears in place of B. There is no right shifting capability; however, an RTM subroutine can be written to do this. On the plus side, data can be written simultaneously into A and M[X] if desired.

DMar is implemented using a model S54181\N74181 Integrated Circuit which has the capability of implementing 16 arithmetic functions and 16 Boolean functions of the 2 input variables (in this case. A, and M[X]). The functions can be evoked in either of two ways: direct (e.g., <- A, <- M[X],..., <- A + M[X]); or encoded, in which the 5-bit code at M __[]__ S<3:0> determines the operation. When used in the encoded mode, the code inputs must be present only during the desired operation and not at other times. Again, the NOR gates that are provided can be used to expand these inputs. The operations using this mode are given in Figure 25 for the logic case (m=0) and the arithmetic case (m=1). Whenever the code HHHHH (for all High) is used, the readout signal, <-f, on the DMaru must be separately evoked (see Figure 24). For all other functions (direct or encoded) <-f is automatically evoked via the Common read-out signal from the Kfe. Whenever the encoded evoke is used, the C input must be used to specify the Carry In to the DMaru. For direct evokes, the Carry In is specified automatically, e.g. on <-A*2 it takes the value of LSI, just as it does in the DMgpa.

__K(bus control and termination combined)\Kbusc__. Kbusc (see Figure 26) is a simplified version of the Kbus and the Bus terminator within a single (double height) board. Kbusc has no Bus Sense Register, although the result given in the most recent transfer on the Bus can be monitored via the following signals: DZ\(result = 0); DN\(result < 0); DP\(result > 0); and OVF\OVERFLOW. The evoke input signals: Bus <-, <- 0, and Set OVF are also available. The above signals and the four basic switch inputs: POWER CLEAR\PC, AUTO-MANUAL, SINGLE STEP and START are identical to those of Kbus.

In addition, Kbusc has the following outputs that Kbus doesn't have:

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