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In a similar way, one of 29 Boolean (bit) input conditions (three of the possible conditions are reserved) can be sensed using the switch input structure. This function is:

With this function the branch-code selects one of 29 Booleans to test. The final part of the structure is the K(interpreter) which controls the action

of the other parts and forces the system to take on the desired behavior (see Figure 22). Note the behavior is expressed using a flowchart with register transfer operations. It is not an RTM system because it is not implemented with RTM parts, although it could be built in this fashion. The behavior is very similar to that of a general purpose stored program computer in that the interpreter picks up instructions sequentially (fetching), examines them (decoding), and then executes them. The execution process consists of taking one of four alternatives, depending on the instruction code. These alternatives correspond to evoke, conditional branch, subroutine call, and subroutine return, respectively. It is implicit in the execution of the evoke instruction that the ((interpreter) waits for a Bus DONE signal before proceeding.


Figure 23 shows the microprogram which computes the sum of integers to N. The program begins in location 0. Here, each operation is assigned a location in the memory in sequence. The convention for interpretation is that each instruction is picked up sequentially from memory. The sequence is broken by the final branch instruction, which returns control back to location 2. Note that the serial merge corresponds to a branch to a particular location. To convert the above microprogram to a microprogram subroutine only requires a subroutine return instruction in location 6. Doing this implies that location 0 is the beginning of the subroutine, i.e., a subroutine call 0 instruction specifies the function as a subroutine.

By looking at the previous example and structure of the microprogrammed controller, the reader may have some idea of its intended use. Whereas the hardwired structure can provide for parallelism in the control structure behavior, the microprogrammed control operates in a completely sequential fashion; each step is at least one access to the memory. Although the K(PCS) gives up parallelism, the cost is considerably less than that of a conventional RTM control part for larger systems. Also, the user commits himself to a fixed memory structure with the microprogrammed controller, whereas the hardwired structure can be modified somewhat. In Chapter 4 a graph is given for the cost of the control part versus the number of control, steps for hardwired and K(PCS) implementations. The cross-over point for K(PCS) is approximately 80 control steps.

Chapter 6 presents the PDP-16/M computer which uses K(PCS) in a fixed


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