Bus, respectively. These two fields can map the bits of the R register onto the selected half of the bus in any configuration. All unmapped bits can be wired to fill either 0's or l's. Either one or both of the write operations can be evoked simultaneously. The same applies for the read operations. However, one cannot both read and write the same Mtr simultaneously.

Each bit of the R register is available as a Boolean output. The D(decoder) is often used with the P register to decode its contents. By using the Boolean DA disable input (see DMflag explanation) a register transfer can be made to multiple Mtr's at the same time, e.g. A <- B <- C <- D, where A, B, and C are all Mtr's and all registers (A,B,C, and D) are connected to the same Bus. The effect is; A <- D; B <- D; C <- D. The same caveat applies for zeroing the DA disable input here as applied for the DMflag. In addition, special wiring, not specified in the PDP-16 handbook, must accompany the Mtr, whether the DA disable is used or not. (See the pin number in Table 5.)

M(byte register)\Mbyte. The M(byte register) is similar to the Mtr, except it only has one write operation, R<-, and it has 4 read operations, Bus<3:0> <- R<f 1>, Bus<7:0> <- R<f 2>, Bus<11:0> <- R<f3>, and Bus<15:0> <- R<f4>. There is no DA disable on the Mbyte.

M(array;1024 word). This M is a 1,024 word, random access, solid state memory, declared A[0:1023]<15:0>. It allows (indirect) expressions of the form <- A[X] and A[X] <-, for reading and writing, respectively. In order to specify the location in memory, the address, X, is first loaded into the memory address register, MA, by the operation MA <-. In fact sometimes we shall use these latter forms for the operations rather than the former. In addition, we sometimes use <-M[MA) and M[MA]<- (where M simply stands for Memory), or we use e.g. <-CHP or Unbinned-item-count<-, where CHP and Unbinned-item-count are aliases for specific memory locations. These different forms reflect the different ways that one can think about memory access.

Once the memory address has been specified, a command to transfer data is given. The data is transferred in or out of the Data register which is the interface to the storage part of the memory. Thus the two commands are <- Data and Data <- for reading and writing, respectively, which correspond to ,- A[MA] and A[MA]<-.

M(array; read only; 1024 word). This is a 1,024 word braided wire, read only memory. It is similar to the previous M in behavior, except it does not allow write operations. This module required special interface to the PDP-16 system (see the PDP- 16 handbook).

M(array; 256-word). This M is just like the M(array; 1024-word), except it has fewer words.

M(scratchpad; 16 words). This memory is an array of 16 temporary storage registers, S[0:15]<15:0>, which are essentially considered independently. The individual words are selected by one of 15 operation inputs, S[i] for I=0,1,...14, and these are accompanied by a read or a write input. If no operation input is selected, S[15] is selected. Only one register can be used at a time.

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