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Chapter 3l System design of a FORTRAN machine 381

CHANGE STATE

State 2 and NO MATCH

CHANGE STATE

State 5 and Sv

DECREASE STC

STC® MAR

READ

CHANGE STATE

State 5 and d

DECREASE STC
DECREASE STC
DECREASE STC

SCIO ® CIO

CIO® MAR

READ

CHANGE STATE

In state 0 of Fig. 4 a START VMU signal takes it to state 1. This is accomplished by the top AND of Fig. 6. The only microstep needed is CHANGE STATE. In state I of Fig. 4, the next clock pulse (after reaching state 1) causes a transition to state 2. In this case we need to save CIO contents in register SCIO, (CIO ® SCIO) set the STC to 4095 (4095 ® STC shown above in BCD form) and get the contents of the address now in the Symbol Table Counter (READ(STC)). This latter is implemented by the two microsteps STC ® MAR followed by a READ command to the core memory. This transition from 1 to 2 of Fig. 4 is accomplished by the next 5 AND gates shown in Fig. 6. The next AND gates shown accomplish the transition from state 2 to 3 if there is a MATCH. The next AND accomplishes the transition from 2 to 8 if there is NO MATCH (in this case nothing need be done). Finally the lowest two groups of AND gates implement the required microsteps as the circuit changes from state 5 to 7 if a 4-bit digit code is sensed or causes the circuit to remain in state 5 after decrementing the STC if an 8-bit variable code is read.

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