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342 Part 4 The instruction-set processor level: special-function processors

Section 3 Processors defined by a microprogram

The volume available, together with the schedule, required a logical design with natural packaging properties in the sense that it should break, in a natural way, into logical packages of a reasonable size having a minimum of interpackage communication.

Design decisions

The need for 2000 operations per second poses a serious access problem with a serial memory, unless one resorts to several simultaneously operating control units which are neither small nor simple. Hence, a random access memory seemed advisable. Magnetic core memories at 85° C are a problem, but they can be built. provided memory cycle time is not too short. The memory was chosen as 4096 words of core storage, with a 20-m sec cycle time.

The requirement for training a man in two weeks to maintain the machine argues for a simple-structured parallel machine. Providing that much use is made of asynchronous transfer, there are a variety of simple maintenance methods, particularly if a bus structure is adopted. Also, asynchronous, or semi-asynchronous, parallel machines require only average performance of a set of components, not of any particular component; the central limit theorem of statistics can come to the aid of reliability. This approach was finally adopted.

The simplicity of both design and understanding is aided by the use of a microprogram control system. Further, maintenance is made rather simple by two provisions on the maintenance console.

The first of these is a manner of going through the microprogram on a step-by-step basis. While this tests little of the dynamics, it can often locate totally defective parts, and it helps factory checkout immeasurably.

The second is a means of taking out the microprogram unit and substituting a set of switches. This permits a maintenance man to exercise specific registers, or the memory, at will.

This is a powerful tool, and is almost free with a microprogram control. Finally, and rather pragmatically, microprogramming permits "last minute" changes in machine operation without serious hardware modifications. This approach was chosen.

Regardless of the control used, at various times in the process of executing orders, decisions must be made. Occasionally these are on a single bit, more often on two, and occasionally on more than two. If one excludes order decoding, only such functions as zero detection require the use of more than two bits. At this point, the logical designer is faced with a rather sticky decision: whether to -design a specific set of decision logic, which is cheap to build but sometimes messy, or to use some microcontrolled logic- generating scheme.

In this case, the latter alternative was taken. A unit, called (for several obscure reasons) the alteration unit, was designed which amounted to a three-address, one-bit unit. It can generate any Boolean function of two binary variables and transmit this value to another variable. A special set of logic was needed for detecting zeros.

Because of the rather wild nature of the inputs, it seemed desirable to include a trapping mode. The logic for this was made an adjunct to the alteration unit.

The circuitry chosen was resistor-transistor logic, which yields either Sheffer stroke or NOR logic, as one prefers, high or low true logic, and p-n-p or n-p-n transistors. In this case, the combination was high true logic and p-n-p transistors, so that the logical operation is Sheffer stroke. Because of temperature and reliability requirements, the maximum frequency available was a 250-kc square wave. This gave a cycle time of 4 m sec available for asynchronous transfer in any sequence of logic.

An index register seemed advisable because of the amount of data processing. Thus, additions were needed for indexing, arithmetic, and counter advance. It seemed undesirable to have more than one parallel adder, so that an adder accessible to all registers was chosen. This was another argument for a bus structure.

Because of the multiplicity of problems being handled simultaneously, one index register was not really enough. Rather than add another register, indirect addressing was chosen.

At this point, one needs 12 bits for address, one for index tagging, and one to specify whether the address is direct or indirect, or 14 bits for operand selection. Thirty-two orders was a tight minimum, so the minimum word length was 19 bits. Since this was consistent with five decimal place accuracy, it was tentatively chosen. It was decided, however, to design a structure basically suited to any length word.

Shifting is necessary to multiply and divide and is required on two registers, yet shift registers for asynchronous operation are complex. Hence, it was decided to put the shift facility on the data transfer bus. By providing complementing here, subtraction could be generated.

It was decided to use two-complement arithmetic, first because of the simplicity of the multiply-divide logic, and second because it avoids the whole negative zero question.

The precise number of microsteps needed was determined by a trial microprogram. The machine was designed for up to 512 microsteps although only 384 are now used. Eight bits were in

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