290 Part 3 The instruction-set processor level: variations in the processor
Section 6 Processors with multiprogramming ability
Fig. 8. Limit imposed by cycle time on operating speed for different divisions of the core store.
are several stacks instructions and operands are separated wherever possible. Under these conditions it is possible to calculate the limit imposed on the operating speed by the cycle time for different divisions of the core store. The results are shown in Fig. 8, for stacks arranged in pairs instructions are read in pairs and in all cases both instructions and operands are assumed to be on the core store. Operands are assumed to be selected at random from the operand space, for instance in the case of two stacks arranged as a pair, successive operand requests have equal probability of being to the same stack or to alternate stacks.
The limit imposed by a four stack store is never severe compared with other limitations, for example the sequence of floating point addition orders discussed in Sec. 4 required 1.6 m sec per order with ideal distribution of instructions and operands. Division into eight stacks, although it reduces the limit, will not have an equivalent effect on the over-all operating speed, and such a division was not considered to be justified.
References
KilbT62; BrooR60; EdwaD60; KilbT56; 60a, 60b, 61; LonsK56; PapiW57; FotbJ61; HartD68; HowaD61; 62, 63; MorrD67; SumnF62