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156 Part 2 The instruction-set processor: main-line computers

Section 1 Processors with one address per instruction

The conversion of a 15-bit address into a bank number and an ambiguous 12-bit address is as follows: the top 5 bits correspond directly to the desired bank number. The remaining lower-order 10 bits, logically added to octal 6000, form the proper ambiguous address. If the 15-bit address is less than octal 6000, however, the address is in erasable or fixed-fixed memory. In this case the logical addition of octal 6000 is suppressed.

It is possible to have a program in one bank call a closed subroutine in another bank, and then have control returned to the proper place in the bank of origin. This is done by means of a short bank switching routine which is in fixed-fixed memory.

One potential awkwardness about this method of extending memory addresses is the possible requirement for a routine in one bank to have access to large amounts of data stored in another. There are many programming solutions to this problem, obviously at a cost in operating speed; a better solution would be to have two bank registers. No problems of this nature have yet materialized, however.

References

AlonR63; AlonR60; AlonR6l; AlonR62; BeckF6l; CasaC62; EnglW62; HopkA63; MuntC62: RichR55; WaleW62: Proc. Conf. Spaceborne Computer Eng.; Anaheim. Calif., Oct. 30-31, 1962.

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