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122 Part 2 The instruction-set processor: main-line computers

Section 1 Processors with one address per instruction

to its contents. (That is, there is a side effect to referencing.) Thus, address integers in the register can select the next member of a vector or string for accessing.

The instruction-set-execution definition can also be presented as a decoding diagram or tree (Fig. 2). Here, each block represents an encoding of bits in the instruction word. A decoding diagram allows one more descriptive dimension than the conventional, linear ISP description, revealing the assignment of bits to the instruction. Figure 2 still requires ISP descriptions for Mp, Mps, the instruction execution, the effective-address calculation, and the interpreter. Diagrams such as Fig. 2 are useful in the ISP design to determine which instruction numbers are to be assigned to names and operations and instructions which are free to be assigned (or encoded).

There are eight basic instructions encoded by 3 bits, that is opá 0:2ñ : = iá 0:2ñ , where instruction/iá 0:11ñ . Each of the first six instructions (where 0 £ op < 6) have the 4 address operand determination modes (thus yielding essentially 24 instructions). The first six instructions are:

data transmission: deposit and clear-accumulator/dca two's complement add to the accumulator/tad

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