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520 ISPS PRIMER FOR THE INSTRUCTION SET PROCESSOR NOTATION

Memory State

The description of the PDP-8 begins by specifying the primary memory that is used to store data and instructions:

M\Memory[0:4095]<0:1 1>,

The primary memory is declared as an array of 4,096 words, each 12 bits wide. The memory has a name (M) and an alias (Memory). These aliases are a special form of a comment and are useful for indicating the meaning or usage of a register's name. As in most programming languages, ISPS identifiers consist of letters and digits, beginning with a letter. The period character (.) is also allowed, to increase the readability. The expression [0:4095] describes the structure of the array. It declares the size (4,096 words) and the names of the words (0,1,..., 4094,4095).

The expression <0:11> describes the structure of each individual word. It declares the size (12 bits) and the names of the bits (0,1,...,10,l1).*

Memory is divided into 128-word pages. Page zero is used for holding global variables and can be accessed directly by each instruction. Locations 8 through 15 of page zero have the special property called auto indexing: when accessed indirectly, the content of the location is incremented by 1. These regions of memory can be described as part of M as follows:

The word (and bit) naming conventions on the left-hand side of a field declaration are independent from the word (bit) names used on the right-hand side. A.I[0] corresponds to M[8], A.I[1] corresponds to M[9], and so on.

Processor State

The processor state is defined by a collection of registers used to store data, instructions, condition codes, and so on during the instruction interpretation cycle.

The PDP-8 has a 1-bit register (L) which contains the overflow or carry generated by the arithmetic operations, and a 12-bit register (AC) which contains the result of the arithmetic and logic operations. The concatenation of L and AC

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* It should be noted that bit and word "names" are precisely that, i.e., identifiers for the subcomponents of a memory structure. These "names" do not necessarily indicate the relative position of the subcomponents. Thus, R<7:3> is a valid definition of a 5-bit register. The fact that the five bits are "named" 7,6,5,4, and 3 should not be confused with the 7th, 6th, etc., positions inside the register. Thus, bit 7 is the leftmost bit, bit 6 is located in the next position toward its right, etc., while bit 3 is the rightmost bit.

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