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is made possible by a set of reserved instructions which cause branching to a fixed micro-address. These reserved instructions cause an illegal instruction trap to occur if user microcode is not present.

Address Space. Like other microcomputers without memory mapping facilities, the LSI-l1 virtual and physical address spaces are the same, both being 16 bits, or 64 Kbytes. (Since two 8-bit bytes make one 16-bit word, this is equivalent to 32 Kwords.) As in other members of the PDP-l1 family, the top 4 Kwords of the address space are normally reserved for peripheral device control and data registers. Thus the nominal maximum main memory size is 28 K 16-bit words.

Interrupt Structure. The LSI-l1 interrupt structure is a subset of the full PDP- 11 interrupt system. Like other PDP-11 processors, the LSI-11 features arbitration between multiple peripheral devices and automatic-service routine "vectoring." It differs, however, in having only a single interrupt level. Interrupts on the LSI-l1 are either enabled or masked, these states being equivalent to PDP-l1 processor levels 0 and 4. With this exception, however, interrupt operation follows the same familiar sequence. Upon acknowledging an interrupt request, the processor stores the current processor status word (PSW) and program counter (PC) on the stack and picks up a new PSW and PC from a memory location (vector) specified by the interrupting device.


PMS Level Description. The "organization" of a computer system denotes the collection of building blocks that comprise it, and the logical and physical links that connect them. A block diagram of the LSI-l1 organization is shown in Figure 2. The LSI-11 CPU, being a microprogrammed processor, is partitioned logically and physically into three main sections - data path, control logic, and micromemory. Each of these units is, in fact, a separate LSI chip. Interconnection of these chips is through the microinstruction bus (MIB).

The Data Chip. The data chip contains an 8-bit register file and arithmetic logic unit (ALU). The chip also provides a 16-bit interface to the data/address lines (DAL) upon which the external LSI-11 bus is built.

The register file consists of 26 8-bit registers; of these registers, 10 may be addressed directly by the microinstruction, 4 may be addressed either directly or indirectly, and the remaining 12 may be addressed only indirectly. Indirect ad dressing is accomplished by means of a special 3-bit register known as the G register, which may be easily loaded from the register address field of the PDP-l 1 instruction. Addressing of the register file is illustrated in Table 2.

The 12 indirectly addressed 8-bit registers are used to realize the 6 PDP-l1 general purpose registers, R0 through R5. The 4 registers which may be addressed either directly or indirectly

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