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THE PDP-8 AND OTHER 12-BIT COMPUTERS 179

Figure 6. The PDP-5.

construction for the Accumulator, Memory Address, and Memory Buffer registers. The analog nature of the initial application was addressed by building an analog-to-digital converter into the Accumulator, thus providing this capability at extremely low cost. The other part of the design that addressed cost was the use of an I/O Bus instead of the radial structure that had been used in the 18-bit designs. The I/O Bus permitted equipment options to be added incrementally from a zero base instead of having the pre-allocated space, wiring, and cable drivers that characterized the radial structure. This lowered the entry cost of the system and simplified the later reconfiguring of machines in the field.

Although the design was optimized around the 4-Kword memory, the PDP-5 ultimately evolved to 32-Kword configurations using a memory extension unit. Similarly, although the base machine design did not include built-in multiply and divide functions, these were added later in the form of an Extended Arithmetic Element. While the PDP-5 was designed for real time and control, the aspirations for it to be used generally in a system can be clearly seen in an early photograph (Figure 6).

THE PDP-8

While the PDP-5 had been a reasonably successful computer, it soon became evident that a new machine capable of far greater performance was required. A new series of modules, the Flip Chip series, was being developed for the PDP-7 and for the new version of the PDP-5. The new logic promised a substantial speed improvement, and new core memory technology was becoming available that would permit the memory cycle time to be shortened from 6 microseconds in the PDP-5 to 1.6 microseconds in the new machine. In addition, the cost of logic was now low enough so that the program counter could be moved from the memory to a separate register, substantially reducing instruction execution times. The new machine was called the PDP-8 (Figure 7).

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